Abstract:
The advances in Silicon technology have driven the MOSFET device fabrication towards submicron regime. This work presents simulated results where gate dimensions are determined and associated parameters are defined. NMOSFET with gate lengths 100Å, 65Å, 42.25Å, 27.27Å and 17.85Å, gate width of 100Å and with oxide thickness of 2Å were studied. All the simulations were done using MATHCAD and the results obtained were then used to plot characteristic curves and the transfer curves using ORIGIN lab software. From the results of characteristic curves it was observed that at VG=0V there was no conducting channel between the source and the drain. When a small V D is applied, and as long as the VD is small, enough not to cause any significant difference in the surface potential near source and drain, the electron concentration throughout the channel remains the same and channel behaves like a resistor. As VD is increased the potential drop across the channel reduces the voltage between the gate and the inversion layer near the drain and as a result the electron concentration in the channel near drain decreases causing increase in the channel resistance and therefore ID-VD bends. When gate bias was increased from VG1 to VG2 (where VG represents the gate voltage) it causes an increase in the inversion layer charge and hence channel resistance reduces causing a larger drain current for a given VD. As the dimensions are scaled down, the drain current increases, evidence that sub-micron devices have better performance as compared to un-scaled devices. It can also be noted that there is a strong correlation between device dimensions and device performance. This shows that sub-micron device has better performance as compared to un-scaled device.
